1. Field of the Invention
The present invention relates to a delay circuit in which a plurality of variable delay circuits for giving delays of variable width x.times.2.sup.n with variable step x are provided in parallel and each of the variable delay circuits receives one input signal to produce optional delay to each outputs.
2. Prior Art
A conventional delay circuit is generally constructed as shown in FIG. 4. In FIG. 4, denoted by g.sub.1 through g.sub.m are variable delay circuits which receive one input signal A in parallel. These variable delay circuits g.sub.1 through g.sub.m have the same construction and comprise delay circuit elements a.sub.11 through a.sub.1m for a delay x, delay circuit elements a.sub.21 through a.sub.2m for a delay x.times.2.sup.1, delay circuit elements a.sub.31 through a.sub.3m for a delay x .times.2.sup.2, . . . , and delay elements a.sub.n1 through a.sub.nm for a delay x.times.2.sup.n-1. An input and an output of each delay can be optionally selected by selectors SELs e.sub.11 through e.sub.nm, and each selected output is supplied in series.
That is, the delay circuit elements a.sub.11 through a.sub.1m for the delay x can delay the input signal by the variable step x, the delay circuit elements a.sub.21 through a.sub.2m for the delay x.times.2.sup.1 can delay the input signal by the variable step x.times.2.sup.1, the delay circuit elements delays a.sub.31 through a.sub.3m for the delay x.times.2.sup.2 can delay the input signal by the variable step x.times.2.sup.2, and the delay circuit elements a.sub.n1 through a.sub.nm for the delay x.times.2.sup.n-1 can delay the input signal by the variable step x.times.2.sup.n-1.
The variable delay circuit g.sup.1 realizes a variable delay circuit giving delays of variable width x.times.2.sup.n with variable step x by determining whether it selects or does not select a delay x by the SEL e.sub.11, a delay x.times.2.sup.1 by the SEL e.sub.21, a delay x.times.2.sup.2 by the SEL e.sub.31, . . . , and a delay x.times.2.sup.n-1 by the SEL e.sub.n1. Likewise, the variable delay circuits g.sub.2 through g.sub.m have respectively the circuits equivalent to the variable delay circuit g.sub.1, and it can determine the delay of the equivalent variable width with the equivalent variable step.
As mentioned above, each of the delay circuit elements has been conventionally controlled to be selected with respect to the variable delay circuits g.sub.1 through g.sub.m so that m delay signals A-1 through A-m are produced wherein they are respectively varied in the delay from the input signal A. However, in the conventional circuit arrangement, there is a drawback that each variable delay circuit is large-scaled to increase the variable width. There is another drawback that variable delay circuits are required by a number obtained by multiplying the number of delay signals to be produced to increase the number of delay signals to be produced, leading to large-scaling of each variable delay circuit.
As mentioned in detail above, there are drawbacks in the conventional delay circuit that each scale of the variable delay circuits is enlarged in proportion to the variable width to increase the variable width, and the variable delay circuits are required by a number to increase obtained by multiplying a number of signals to be produced and the number of delay signals to be produced, which leads to large-scaling of each variable circuit.